Patsoft engineers have experience on ASIC design and development for 110nm, 90nm, 65nm and 45nm technologies from architecture desgin to prototype design. Patsoft engineers also have experience on SOC designs.
Patsoft has the following technology expertise for the the ASIC design flow
1. Languaged based hardware design using Verilog
2. ASIC design synthesis using synopsys Design Compiler, Design Compiler expert, Design Compiler
Ultra, and Power Compiler
3. Formal verification using Synopsys Formality
4. Static Timing Analysis using Synopsys Prime Time
5. ECO modification
6. Board level verification of the ASIC chip
Patsoft design engineers have full knowledge of design methods and techniques for both Xilinx and Altera libraries